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march 2012 doc id 022635 rev 1 1/15 AN4030 application note gate to cathode capacitor, impact on triac immunity and reliability introduction triacs and scrs are power semiconductors which are usually directly connected to the grid line. as is well known, the ac grid voltage can be highly perturbed by important voltage variation during very short times, for example, mechanical relay contact bounce, universal motor disturbances. several electromagnetic standards describe how appliances have to be tested to check their immunity to such events. for example, the iec 61000-4-4 standard gives the test procedures and immunity require ments respectively for fast transient voltages. to increase power-semiconduc tor device immunity, most designers add a capacitor across the power device control terminal (the gate for scrs or triacs) and its reference terminal (k or a1 respectively for scrs and triacs). this capacitor helps stabilize the control terminal potential and so is believed to help increase resistance to fast voltage rises (dv/dt). as this capacitor is also placed between the power de vice and the control circuit, which could be a logic gate or a microcontroller unit (mcu), it acts as a filter on the path from the line to the sensitive control circuit, and helps filter the noise coming from line disturbances. this paper demonstrates why a gate to cathode capacitor is not efficient to improve triac immunity to fast voltage transients, especially for non-sensitive devices. this application note demonstrates that such capacitors can increase the risk of failure for repetitive or accidentally high di/dt. the results presented in this application note have been produced over a considerable period of time. some products, which are used as examples to present these results, may no longer be available. however, the results presented apply to classes and types of product, and thus are equally applicable to similar products available in the market. www.st.com
contents AN4030 2/15 doc id 022635 rev 1 contents 1 gate to cathode capacitor, impact on dv/dt im munity . . . . . . . . . . . . . 3 1.1 dv/dt test method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 dv/dt improvement for scr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 behavior of triacs regarding dv/dt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.4 behavior of triacs to eft (electrical fast transient) . . . . . . . . . . . . . . . . . . 8 2 gate to cathode capacitor, impact on di/dt capability . . . . . . . . . . . . . 11 3 conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
AN4030 gate to cathode capacitor, impact on dv/dt immunity doc id 022635 rev 1 3/15 1 gate to cathode capacitor, impact on dv/dt immunity 1.1 dv/dt test method to characterize device immunity, semiconductor companies give the maximum dv/dt rate which can be applied across a device without a risk of triggering it. the test schematic features a dv/dt generator which applies a voltage-versus-time linear slope (see figure 1 ). the test equipment detects if the voltage across the dut (device under test) decreases below a given threshold. for a given dv/dt level, if the device voltage drops below this threshold, th is means that the de vice has switched on . the dut capability is then lower than this dv/dt rate. the dv/dt parameter specified in the device datasheet is then the minimum rate that all devices were able to withstand during the tests. figure 1. dv/dt test simplified schematic the dv/dt parameter is usually measured under the following conditions: peak applied voltage = 67% of v drm maximum junction temperature (125 c most of the time) gate open these test conditions are the worst case, as the dv/dt immunity decreases if both the junction temperature and the impedance between g and k increase. the following figures give an example of a 600 v scr dv/dt measurement. a 402 v peak voltage is applied, as it repr esents 67% of the specified v drm . in figure 2 , the device remains off. there is no current increase. in figure 3 , the same device switches on approximately 2 s after the voltage reaches its peak and stable level. according to these two results, it could be said that the tested scr is able to withstand a 150 v/s rate. + - dv/dt generator (lemsys 50) 20 t v dv/dt v peak gate to cathode capacitor, impact on dv/dt immunity AN4030 4/15 doc id 022635 rev 1 figure 2. c test with a 150 v/s slope figure 3. 600 v scr test with a 160 v/s slope 1.2 dv/dt improvement for scr to understand why a semiconductor can be triggered by a dv/dt slope applied across its terminals, it should be kept in mind that semiconductor devices are composed of several silicon layers. an scr features four layers, al ternatively doped by holes (p area) or by electrons (n area). each pn junction presents a spurious capacitance (see figure 4 ). when a voltage slope is applied, a spurious capacitive current (i cap ) is induced by these capacitances. this current can then flow to the cathode through the p1-n1 junction and cause device switch-on. to solve this issue, an impedance, for example a resistor (refer to gate to cathode resistor in figure 4 ), could be added between the gate and cathode terminals. the spurious capacitive current is then shunted and avoids the device being triggered. 402 v v t i t 402 v v t i t
AN4030 gate to cathode capacitor, impact on dv/dt immunity doc id 022635 rev 1 5/15 figure 4. scr simplified silicon structure and spurious capacitive current a better solution could be found if a capacitor is used instead of a resistor. a high-voltage gate to cathode capacitor is not necessary because only a low voltage (v gk is around 1 v typically) is applied across this capacitor. figure 5 shows the typical relative dv/dt increase versus gate-cathode capacitance for an 8 a sensitive scr series (i gt max = 0.2 ma). the scr dv/dt could be improved more than ten times with a 100 nf gate to cathode capacitor. it should be noted that a gate to cathode resistor is still us ed in parallel with the gate to cathode capacitor to discharge it after gate current removal. for non?sensitive scrs (i gt above around 5 ma), a gate to cathode capacitor does not improve dv/dt immunity a lot. indeed, these devices already feature a very low internal gate to cathode resistor. so adding any external component is not very efficient to shunt the spurious capacitive current. n1 p2 n2 p1 cathode (k) gate (g) anode (a) c n1/p1 c p1/n2 c n2/p2 r gk i cap
gate to cathode capacitor, impact on dv/dt immunity AN4030 6/15 doc id 022635 rev 1 figure 5. scr dv/dt increase versus added gate to cathode capacitor 1.3 behavior of triacs regarding dv/dt a triac silicon structure differs from an scr stru cture. first, triacs can conduct current in both directions. a triac is equivalent to 2 scrs back-to-back with a common gate. the real gate area of the reverse scr is on the opposite side of the gate terminal connection (see figure 6 ). figure 6. triac simplified silicon structure this device can turn on with dv/dt slope in direct or in reverse. when a positive dv/dt static is applied on a2, the device scr1 can improve its immunity with a gate to cathode capacitor or gate to cathode resistor. with this polarity the device is equivalent to an scr. it?s really efficient for a sensitive triac which has a high value internal r1 gk (see figure 7 ). the external gate to cathode capacitor or gate to cathode resistor is then in parallel and improves immunity. when the positive dv/dt slope is applied on a1, ther e is no possibility to reinforce this immunity. the gate electrode is on opposite side and ther e is no possibility to add an external component in parallel with internal r2 gk . dv/dt [c gk ] / dv/dt [r gk = 220 ] 0.0 2.5 5.0 7.5 10.0 12.5 15.0 0 20 100 160 200 c gk (nf) v d = 0.67 x v drm t j =125 c r gk =220 40 60 80 120 140 180 n3 n1 p2 n2 p1 n4 a2 a1 g p2 n2 p1 g k a scr1 a k scr2
AN4030 gate to cathode capacitor, impact on dv/dt immunity doc id 022635 rev 1 7/15 figure 7. triac simplified silicon structure with internal gate to cathode resistor shown the gate to cathode capacitor thus has a totally different impact according to the bias voltage. ta bl e 1 and ta bl e 2 give, for example, some dv/dt characterization results respectively for one triac (16 a, 600 v, 10 ma i gt device) and for another triac (16 a, 600 v, 35 ma i gt device). for the more sensitive device (i gt = 10 ma), a 100 nf gate to cathode capacitor improves the dv/dt capability by a factor of 10, but only for positive voltage bias. for the other devices (i gt = 35 ma), the 100 nf gate to cathode capacitor does not have any impact on the dv/dt capability. so a gate to cathode capacitor could be useful only for sensitive devices, but only for half the time for appliances working on ac voltage. experiments have shown that a gate to cathode capacitor could improve the immunity level during iec 61000-4-4 standard tests for the more sensitive device (i gt = 10 ma) but not for the 35 ma i gt device, as shown in section 1.4 . table 1. dv/dt characterization @ 125 c and v peak = 402 v for sensitive triac device (i gt = 10 ma) without gate to cathode capacitor with gate to cathode capacitor (100 nf) sample 1 sample 2 sample 1 sample 2 dv/dt (v/s) direct 360 450 2260 1900 reverse 800 760 800 760 n3 n1 p2 n2 n4 a2 a1 g n2 p1 internal r2 gk internal r1 gk
gate to cathode capacitor, impact on dv/dt immunity AN4030 8/15 doc id 022635 rev 1 1.4 behavior of triacs to ef t (electrical fast transient) to compare immunity between several triacs (snubberless and logic level) with and without gate to cathode capacitor, tests have been carried out in the following conditions (see figure 8 ): an x2 1nf capacitor is connected at line input. the pcb is 10 cm above the reference plane. the triac a2 terminal is linked to a 25 w light bulb (resistive loads are chosen in order to reduce di/dt rates in case of firing). the gate could be left open, or connected to a1 terminal through an external gate to cathode capacitor or connected to a1 through a 100 r g in series with a gate to cathode capacitor. no snubber circuits are added across the triacs. ambient temperature: 25 c. the burst generator is programmed as required in the iec 61000-4-4 standard (15 ms burst duration, 3 hz burst frequency, 5 khz spike frequency, one second test duration). table 2. dv/dt characterization @ 125 c and v peak = 402 v for less sensitive triac device (i gt = 35 ma) without gate to cathode capacitor with gate to cathode capacitor (100 nf) sample 1 sample 2 sample 1 sample 2 dv/dt (v/s) direct 2350 1850 2350 1850 reverse 2750 1950 2750 1950
AN4030 gate to cathode capacitor, impact on dv/dt immunity doc id 022635 rev 1 9/15 figure 8. iec 61000-4-4 test configuration ta bl e 3 and ta bl e 4 give the test results for the two previous sample triacs (logic level and snubberless) with and without gate to cathode capacitor. a burst test is carried out for each coupling mode (to line, to neutral, and to line and neutral). only the minimum burst level before turn-on, for all coupling modes, is recorded in these two tables. table 3. iec 61000-4-4 tests results with logic level triac - sensitive device (i gt = 10 ma) without gate to cathode capacitor with gate to cathode capacitor (100 nf) with r g (100 ) and c gk (100 nf) sample 1 sample 2 sample 1 sample 2 sample 1 sample 2 minimum held burst level (kv) 1.3 1.3 3.6 3.5 3.3 3.2 table 4. iec 61000-4-4 test results with snubberless triac - less sensitive device (i gt = 35 ma) without gate to cathode capacitor with gate to cathode capacitor (100 nf) with r g (100 ) and c gk (100 nf) sample 1 sample 2 sample 1 s ample 2 sample 1 sample 2 minimum held burst level (kv) > 4.5 > 4.5 > 4.5 > 4.5 > 4.5 > 4.5 c gk r g 1 nf x2 l n reference plane 10 cm burst generator coupling network pe pe
gate to cathode capacitor, impact on dv/dt immunity AN4030 10/15 doc id 022635 rev 1 these experimental results show that there is no immunity improvement if a gate to cathode capacitor is added to snubberless triacs. indeed, the immunity level is very high and above our burst generator capability (4.5 kv). on the other hand, logic level triacs withstand a lower immunity level compared to snubberless devices. this level is lower without gate to cathode capacitor. a 100 nf gate to cathode capacitor improves almost by 3 the triac immunity. but gate to cathode capacitor lowers triac reliability (refer to section 2: gate to cathode capacitor, impact on di/dt capability ). to keep the gate to cathode capacitor benefits without lo wering system reliability, one solution is then to add a resistor (r g ) in series with gate to cathode capacitor. the immunity level is then similar to that with the single gate to cathode capacitor. such a resistor comes for free, since the gate resistor, used to limit the control circuit output current, can be used as r g . usually, logic level triacs are driven direct ly by a microprocessor. mcu 4-4 immunity behavior is improved by adding an rcr filter. a comparison with and without filter has been performed with an acst (i gt max = 10 ma, 6 a on-state rms current) and an st mcu. a capacitor is connected between 2 resistors and a1. one of these resistors (240 ) is connected to the output of the mcu and the other one (50 ) to the acst gate. this can improve the level of immunity up to 600 v according to coupling, polarity and mcu output configuration. for instance, with an mcu open drain output configuration, negative voltage applied on line, 4-4 immunity is 3.9 kv with a filter compared to 3.3 kv without a filter.
AN4030 gate to cathode capacitor, impact on di/dt capability doc id 022635 rev 1 11/15 2 gate to cathode capacitor, impact on di/dt capability as well as being almost ineffective in improving triac immunity, a gate to cathode capacitor has a major drawback when operating with triacs. a gate to cathode capacitor significantly decreases the triac di/dt capability. for example, ta b l e 5 gives the experimental results obtained in repetitive operation for a standard triac (1 a, 600 v, 5 ma i gt ). ta b l e 5 clearly shows that the lifetime of the device is drastically reduced when a 100 nf or 10 nf gate to cathode capacitor is added. on the other hand, the triac di/dt c apability remains if a resistor is added in series with a gate to cathode capacitor. the high density current during charge and discharge of the capacitor explained the poor life time with a gate to cathode capacitor. in case of an r g -c g circuit, the resistor in series limited this density of current. triac dv/dt immunity is improved with this circuit and di/dt capability is not decreased. figure 9 gives the different operating steps when a triac is switched on in quadrant 2 (v t > 0 and i g < 0) with a gate to cathode capacitor. the event sequence is as follows. 1. the triggering current is first sunk from the gate by the control circuit. 2. the pilot scr is turned on . this pilot scr is implemented by the p2-n2-p1-n4 layers. it is not the same scr that is on at the end of this switching-on process. 3. a high inrush current circulates through the gate to cathode capacitor due to the pilot scr turn-on (without gate to cathode capacitor, the gate current would be limited by the gate resistor r g ). 4. the gate to cathode capacitor is discharged after the main scr turn-on. this scr is implemented by the p2-n2-p1-n1 layers. this causes a high peak gate current and can damage the triac. table 5. repetitive di/dt tests results with a standard 1 a triac without gate to cathode capacitor with gate to cathode capacitor (100 nf) with r g (50 ) and c g (100 nf) di/dt (a/s) 30 30 30 i peak (a) 3.5 3.5 3.5 number of cycles (million of cycles) 50 0.1 50 results 0 failed / 20 8 failed / 10 0 failed / 10
gate to cathode capacitor, impact on di/dt capability AN4030 12/15 doc id 022635 rev 1 figure 9. sequence of events during triac switch-on in quadrant 2 even if the triac is driven in zero voltage switch mode, a spurious turn-on could appear and a high di/dt could run through pilot scr. a gate to cathode capacitor could increase the failure rate as explained above. for example, for the sensitive logic level triac described in section 1.4 , non repetitive di/dt capability robustness in q2 is divided by around 2 with a gate to cathode capacitor: 360 a/s with c gk = 200 nf and 670 a/s without gate to cathode capacitor. this behavior is not linked to the triac technolo gy but directly linked to the internal device. so, whatever the technology, a gate to cathode capacitor will decrease di/dt capability in repetitive or in accidental mode. n3 p2 n2 p1 n1 p2 n2 p1 a2 a1 g - ++ i g i t i c c gk r g 1 2 4 3 n4
AN4030 conclusion doc id 022635 rev 1 13/15 3 conclusion to increase power semiconductor device immunity to fast transient voltages it is quite common to add a capacitor between the control terminal (gate or base) and the drive reference terminal (source, emitter, cathode or a1 terminal). for scrs, the drive reference is the cathode, k. a gate to cathode capacitor is then usually added with very sensitive devices and could be very useful to increase scr immunity to dv/dt. this application note shows that as well as being almost ineffectiv e in improving triac immunity, a gate to cathode capacitor has a major drawback when operating with triacs. such a capacitor increases the failure rate when repetitive di/dt rates are applied at turn-on or in case of spurious turn-on with high di/dt. explanations of silicon structure behavior during turn-on show th e supplementary stress due to a gate to cathode capacitor irrespective of technology choice. this shows that such capacitors should be removed from triac designs.
revision history AN4030 14/15 doc id 022635 rev 1 4 revision history table 6. document revision history date revision changes 27-mar-2012 1 initial release.
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